Modulation apparatus and method

ABSTRACT

The present invention pertains to a modulation apparatus and method in which the modulation apparatus is realized with a simple circuit structure and is easily applicable to other systems. A pattern conversion unit  32  converts data having a basic data length of 2 bits supplied from a DSV control bit determination and insertion unit  31  into a variable-length code having a basic code length of 3 bits in accordance with a conversion table. A minimum-run-length limitation code detection unit  33  detects, from a data sequence containing a DSV control bit, the position of minimum runs consecutive from a channel bit string converted by the pattern conversion unit  32 . A consecutive-minimum-run replacement unit  34  replaces a predetermined portion of the channel bit string supplied from the pattern conversion unit  32  for a predetermined pattern based on the position information supplied from the minimum-run-length limitation code detection unit  33 , and limits the minimum run length to a predetermined number or less. The present invention is applicable to a modulation apparatus.

TECHNICAL FIELD

[0001] The present invention relates to a modulation apparatus andmethod, and particularly to a modulation apparatus and method suitablefor data transmission or recording onto recording media.

BACKGROUND ART

[0002] For transmission of data over a predetermined transmission pathor recording of data onto recording media such as magnetic discs,optical discs, and magneto-optical discs, the data is modulated so as tobecome compatible with the transmission path or the recording media. Oneknown modulation method is block coding. In block coding, a datasequence is divided into blocks of m×i bits (the blocks are hereinafterreferred to as data words) and each data word is converted into acodeword of n×i bits in accordance with an appropriate coding rule. Ifi=1, the code is a fixed-length code. If a plurality of i's areselectable or if conversion is performed using a predetermined iselected from a range of 1 to imax (maximum i), the code is avariable-length code. The block-coded code is expressed as avariable-length code (d, k; m, n; r).

[0003] As used herein, i is referred to as the constraint length; imaxcorresponds to r (maximum constraint length); d indicates the minimumnumber of consecutive “0's” that are inserted between consecutive “1's”,e.g., the minimum run length of “0”; and k indicates the maximum numberof consecutive “0's” that are inserted between consecutive “1's”, e.g.,the maximum run length of “0”.

[0004] When the thus obtained variable-length code is recorded onto anoptical disc, a magneto-optical disc, or the like, for example, in thecase of a compact disc or mini disk, the variable-length code issubjected to NRZI (Non Return to Zero Inverted) modulation in which “1”is inverted and “0” is not inverted, and recording is performed based onthe NRZI-modulated variable-length code (hereinafter also referred to asa recording waveform string). In the initial ISO (InternationalOrganization for Standardization) compatible magneto-optical discshaving relatively low recording density, modulated recording bit stringswhich were not subjected to NRZI modulation were recorded.

[0005] Assuming that the minimum inversion interval of the recordingwaveform string is indicated by Tmin and the maximum inversion intervalof the recording waveform string is indicated by Tmax, a longer minimuminversion interval Tmin or greater minimum run length d is desirable forhigh-density recording in the linear velocity direction, and a shortermaximum inversion interval Tmax or smaller maximum run length k isdesirable in view of clock playback. A variety of modulation methodsmeeting these conditions have been proposed.

[0006] Specific modulation methods proposed or actually used in, forexample, optical discs, magnetic discs, magneto-optical discs, and thelike include a variable-length RLL (1-7) (also expressed as (1, 7; m, n;r)) code or RLL (2-7) (also expressed as (2, 7; m, n; r)) code, and afixed-length RLL (1-7) (also expressed as (1, 7; m, n; 1)) code for usein ISO-compatible MO discs. High-recording-density disc devices such asoptical discs and magneto-optical discs which are being developed andstudied often use RLL codes (Run Length Limited codes) with minimum runlength d=1.

[0007] An example conversion table of the variable-length RLL (1-7) codeis shown as follows: TABLE 1 RLL(1, 7; 2, 3; 2) Data Code i = 1 11 00x10 010 01 10x i = 2 0011 000 00x 0010 000 010 0001 100 00x 0000 100 010

[0008] In this conversion table, symbol x corresponds to “1” when thesubsequent channel bit is “0”, and corresponds to “0” when thesubsequent channel bit is “1”. The maximum constraint length r is 2.

[0009] The parameters of the variable-length RLL (1-7) are (1, 7; 2, 3;2). If the bit interval of the recording waveform string is indicated byT, the minimum inversion interval Tmin expressed by (d+1) T is equal to2 (=1+1) T. Assuming that the bit interval of the data sequence isindicated by Tdata, then the minimum inversion interval Tmin given by(m/n)×2 is equal to 1.33 (=(⅔)×2) Tdata. The maximum inversion intervalTmax given by (k+1) T is equal to 8 (=7+1) T ((=(m/n)×8 Tdata=(⅔)×8Tdata=5.33 Tdata). The detection window margin Tw is expressed by(m/n)×Tdata, the value thereof being equal to 0.67 (=⅔) Tdata.

[0010] In the channel bit strings modulated in accordance with the RLL(1-7) coding shown in Table 1, 2T, namely, Tmin, occurs most frequently,followed by 3T and 4T. In most cases, frequent occurrence of edgeinformation with a short period, such as 2T or 3T, is favorable to clockplayback.

[0011] In contrast, when the recording density in the linear velocitydirection becomes higher, a problem with Tmin arises. Specifically, whenthe minimum run length, namely, 2T, occurs consecutively, the recordingwaveform is easily distorted because the waveform output of 2T issmaller than other waveform outputs and is susceptible to, for example,noise, defocusing, tangential tilt, or the like.

[0012] For high linear density recording, therefore, recording withconsecutive Tmin (2T) is sensitive to disturbance such as noise, andthis may lead to errors during data playback. In such a case, dataplayback errors are often caused by simultaneous shift of the leadingedge and the trailing edge of the consecutive Tmin (2T). In other words,the bit error length becomes longer.

[0013] In recording data onto recording media or transmitting data, thedata is modulated in accordance with a coding scheme compatible with therecording media or transmission path. If the modulated code contains adirect-current component, fluctuation or jitter may be caused in variouserror signals, such as for tracking error in servo control of a discdevice. Therefore, it is desirable that the modulated code contains fewdirect-current components.

[0014] Accordingly, DSV (Digital Sum Value) control has been proposed.DSV is the sum of bits of an NRZI-modulated (namely, level-coded)channel bit string by allocating +1 to the bit string (symbol of thedata) set to “1” and −1 to the bit string set to “0”. Reducing theabsolute value of DSV, which is a measure of a direct-current componentof the code string, that is, performing DSV control, enables suppressionof the direct-current component of the code string.

[0015] The codes modulated in accordance with the variable-length RLL(1-7) table shown in Table 1 are not subjected to DSV control. DSVcontrol is realized by determining the DSV of the modulated code string(channel bit string) at predetermined intervals and insertingpredetermined DSV control bits in the code string (channel bit string).

[0016] Basically, the DSV control bits are redundant bits. In view ofcode conversion efficiency, the fewer the DSV control bits, the better.

[0017] Desirably, the inserted DSV control bits do not cause changes inthe minimum run length d and the maximum run length k. Changes of (d, k)affect recording and playback characteristics.

[0018] Actually, the RLL code must meet the minimum run lengthrequirement, although the maximum run length requirement is notnecessarily met. There are some formats in which patterns exceeding themaximum run length are used for a synchronization signal. For example,the 8-16 code for use in DVDs (Digital Versatile Disks) has a maximumrun length of 11T, but gives 14T, exceeding the maximum run length, tothe synchronization signal pattern portion in order to enhance thedetection performance of the synchronization signal.

[0019] Accordingly, in the RLL (1-7) coding with improved conversionefficiency, for supporting high density recording, it is important tocontrol the minimum run length so that it becomes more suitable for highlinear density and to perform DSV control control as efficiently aspossible.

[0020] For example, Japanese Unexamined Patent Application PublicationNo. 11-177431, filed by the present applicant, discloses a modulationapparatus including DSV control bit insertion means for inserting afirst DSV control bit in a data sequence to generate a first datasequence and for inserting a second DSV control bit in the data sequenceto generate a second data sequence; modulation means for modulating boththe first data sequence and the second data sequence using a conversiontable in which the minimum run length d is 1 and the remainder of thenumber of “1's” in each element of a data sequence divided by two andthe remainder of the number of “1's” in each element of a convertedcodeword string divided by two are equally 1 or 0; and DSV calculationmeans for determining a first sectional DSV of the first data sequencemodulated using the conversion table and a second sectional DSV of thesecond data sequence modulated using the conversion table so that thedetermined sectional DSVs are added to the DSV up to the presentposition and for selecting and outputting, from the resulting DSV, oneof the first data sequence and second data sequence modulated using theconversion table.

[0021]FIG. 1 is a block diagram showing the structure of a modulationapparatus of the related art.

[0022] As shown in FIG. 1, a modulation apparatus 10 includes a DSV bitinsertion unit 11 for inserting “1” or “0”, serving as a DSV bit, intoan input data sequence at predetermined intervals. The DSV bit insertionunit 11 has a data sequence containing the DSV bit “1” and another datasequence containing the DSV bit “0”. A modulation unit 12 modulates thedata sequence in which the DSV bit is inserted by the DSV bit insertionunit 11. A DSV control unit 13 NRZI-modulates the codeword stringsmodulated by the modulation unit 12 to obtain level data, determines theDSV of the level data, and finally outputs a DSV-controlled recordingcode string.

[0023] As another example, Japanese Unexamined Patent ApplicationPublication No. 11-346154, filed by the present applicant, discloses aconversion table including, as a conversion code, a basic code whered=1, k=7, m=2, and n=3; a coding rule that the remainder of the numberof “1's” in each element of a data sequence divided by two and theremainder of the number of “1's” in each element of a converted codewordstring divided by two are equally 1 or 0; a first replacement code forlimiting the minimum run length d to a predetermined number or less; anda second replacement code for meeting the run length limitations.

[0024]FIG. 2 is a block diagram showing the structure of anothermodulation apparatus of the related art.

[0025] As shown in FIG. 2, a modulation apparatus 20 includes a DSVcontrol bit determination and insertion unit 21 for determining a DSVcontrol bit “1”0 or “0” and for inserting the DSV control bit into aninput data sequence at predetermined intervals; a modulation unit 22 formodulating the data sequence containing the DSV control bit; and an NRZIunit 23 for converting the output of the modulation unit 22 into arecording waveform string. The modulation apparatus 20 further includesa timing management unit 24 for generating a timing signal and supplyingthe timing signal to the parts to manage the timing.

[0026] One problem is that the circuit structure of the above-describedmodulation apparatus is complicated. Another problem is that thecomplicated circuit structure makes it difficult to apply the apparatusto other systems.

DISCLOSURE OF INVENTION

[0027] The present invention has been made in view of such a situation,and is intended to provide a modulation apparatus having a simplecircuit structure so that the modulation apparatus can be easily appliedto other systems.

[0028] A modulation apparatus of the present invention includesconversion means for converting input data into codewords in accordancewith a conversion table containing conversion codes having a coding rulethat the remainder of the number of “1's” in each element of the datasequence divided by two and the remainder of the number of “1's” of eachelement of the converted codeword string divided by two are equally 1 or0; minimum-run-length limitation code detection means for detecting aminimum-run-length limitation code from the input data, theminimum-run-length limitation code being contained in the conversioncodes of the conversion table and limiting the minimum run length d to apredetermined number or less; and consecutive-minimum-run replacementmeans for replacing the codeword string converted by the conversionmeans so that the minimum run length is limited to the predeterminednumber or less based on the minimum-run-length limitation code detectedby the minimum-run-length limitation code detection means.

[0029] The modulation apparatus can further include modulationinformation storage means for counting the number of conversionsperformed by the conversion means based on a specified conversion codeof the conversion codes contained in the conversion table and forstoring information indicating the conversion count. Theminimum-run-length limitation code detection means can be controlled todetect the minimum-run-length limitation code from the input data basedon the information stored by the modulation information storage means.

[0030] The modulation apparatus can further include synchronizationsignal insertion means for inserting a synchronization signal containinga unique pattern, which does not exist as a conversion code of theconversion table, at an arbitrary position into the codeword stringwhose minimum run length is limited to the predetermined number or lessby the consecutive-minimum-run replacement means; and NRZI conversionmeans for NRZI-converting the codeword string in which thesynchronization signal is inserted by the synchronization signalinsertion means to generate a recording code string.

[0031] The conversion means can include conversion code detection meansfor detecting a predetermined pattern from the input data, thepredetermined pattern being contained in the conversion codes of theconversion table having a basic code wherein d=1, k=7, m=2, and n=3;termination code detection means for detecting a termination code fromthe input data, the termination code being contained in the conversioncodes of the conversion table and terminating a code at an arbitraryposition; undefined code detection means for detecting an undefined codefrom the input data, the undefined code being contained in theconversion codes of the conversion table and containing an undefinedcode including an undefined character having character “*0*” whichbecomes “000” or “101”, where * denotes “0” if the previous orsubsequent codeword is “1” and denotes “1” if the previous or subsequentcodeword is “0”; undefined bit determination means for determining avalue of the symbol * of the undefined character contained in theundefined code detected by the undefined code detection means; andconversion pattern determination means for determining the conversioncode of the conversion table to be used, based on the detection resultsof the conversion code detection means, the termination code detectionmeans, and the undefined code detection means, and the value determinedby the undefined bit determination means.

[0032] The termination code detection means can include a terminationposition counter which supplies information for specifying thetermination position. The termination code detection means can detect apredetermined pattern contained in the conversion codes of theconversion table from the input data, and can determine that thetermination code is detected when the information supplied from thetermination position counter indicates the termination position.

[0033] The undefined code detection means can acquire informationindicating the last bit of the conversion pattern determined by theconversion pattern determination means and information indicating thelast bit of pattern of the synchronization signal inserted by thesynchronization signal insertion means. The undefined bit determinationmeans can determine the value of the symbol * of the undefined characterbased on the information indicating the last bit of the conversionpattern and the information indicating the last bit of the pattern ofthe synchronization signal acquired by the undefined code detectionmeans.

[0034] The conversion pattern determination means can determine, basedon the termination code, whether or not the conversion pattern inaccordance with which the input data sequence is converted isdetermined. Based on the determination result of the conversion patterndetermination means, the synchronization signal insertion means caninsert the synchronization signal which is subjected to predeterminedprocessing into the codeword string at an arbitrary position.

[0035] In the predetermined processing, the start bit of thesynchronization signal can be set to “1” if the conversion patterndetermination means determines, based on the termination code, that theconversion pattern is determined, and the start bit of thesynchronization signal can be set to “0” if the conversion patterndetermination means determines, based on the termination code, that theconversion pattern is not determined.

[0036] A modulation method of the present invention includes aconversion step of converting input data into codewords in accordancewith a conversion table containing conversion codes having a coding rulethat the remainder of the number of “1's” in each element of the datasequence divided by two and the remainder of the number of “1's” in eachelement of the converted codeword string divided by two are equally 1 or0; a minimum-run-length limitation code detection step of detecting aminimum-run-length limitation code from the input data, theminimum-run-length limitation code being contained in the conversioncodes of the conversion table and limiting the minimum run length d to apredetermined number or less; and a consecutive-minimum-run replacementstep of replacing the codeword string converted by performing theconversion step so that the minimum run length is limited to thepredetermined number or less based on the minimum-run-length detected byperforming the minimum-run-length limitation code detection step.

[0037] The modulation method can further include a modulationinformation storage step of counting the number of conversions performedin the conversion step based on a specified conversion code of theconversion codes contained in the conversion table and controllingstorage of information indicating the conversion count. In theminimum-run-length limitation code detection step, detection of theminimum-run-length limitation code from the input data can be controlledbased on the information stored by performing the modulation informationstorage step.

[0038] The modulation method can further include a synchronizationsignal insertion step of inserting a synchronization signal containing aunique pattern, which does not exist as a conversion code of theconversion table, at an arbitrary position into the codeword stringwhose minimum run length is limited to the predetermined number or lessby performing the consecutive-minimum-run replacement step; and an NRZIconversion step of NRZI-converting the codeword string in which thesynchronization signal is inserted by performing the sync signalinsertion step to generate a recording code string.

[0039] The conversion step can include a conversion code detection stepof detecting a predetermined pattern from the input data, thepredetermined pattern being contained in the conversion codes of theconversion table having a basic code wherein d=1, k=7, m=2, and n=3; atermination code detection step of detecting a termination code from theinput data, the termination code being contained in the conversion codesof the conversion table and terminating a code at an arbitrary position;an undefined code detection step of detecting an undefined code from theinput data, the undefined code being contained in the conversion codesof the conversion table and containing an undefined code including anundefined character having character “*0*” which becomes “000” or “101”,where * denotes “0” if the previous or subsequent codeword is “1” anddenotes “1” if the previous or subsequent codeword is “0”; an undefinedbit determination step of determining a value of the symbol * of theundefined character contained in the undefined code detected byperforming the undefined code detection step; and a conversion patterndetermination step of determining the conversion code of the conversiontable to be used, based on the detection results obtained by performingthe conversion code detection step, the termination code detection step,and the undefined code detection step, and the value determined byperforming the undefined bit determination step.

[0040] The modulation method for the modulation apparatus including atermination position counter which supplies information for specifyingthe termination position can be designed such that, in the terminationcode detection step, a predetermined pattern contained in the conversioncodes of the conversion table is detected from the input data and it isdetermined that the termination code is detected when the informationsupplied from the termination position counter indicates the terminationposition.

[0041] The undefined code detection step can include controllingacquisition of information indicating the last bit of the conversionpattern determined by performing the conversion pattern determinationstep and information indicating the last bit of the pattern of thesynchronization signal inserted by performing the synchronization signalinsertion step. The undefined bit determination step can includedetermining the value of the symbol * of the undefined character basedon the information indicating the last bit of the conversion pattern andthe information indicating the last bit of the pattern of thesynchronization signal acquired by performing the undefined codedetection step.

[0042] In the conversion pattern determination step, it can bedetermined, based on the termination code, whether or not the conversionpattern in accordance with which the input data string is converted isdetermined. In the synchronization signal insertion step, based on thedetermination result obtained by performing the conversion patterndetermination step, the synchronization signal which is subjected topredetermined processing can be inserted into the codeword string at anarbitrary position.

[0043] In the predetermined processing, the start bit of thesynchronization signal can be set to “1” if the conversion patterndetermination means determines, based on the termination code, that theconversion pattern is determined, and the start bit of thesynchronization signal can be set to “0” if the conversion patterndetermination means determines, based on the termination code, that theconversion pattern is not determined.

[0044] A program of a recording medium of the present invention includesa conversion step of converting input data into codewords in accordancewith a conversion table containing conversion codes having a coding rulethat the remainder of the number of “1's” in each element of the datasequence divided by two and the remainder of the number of “1's” in eachelement of the converted codeword string divided by two are equally 1 or0; a minimum-run-length limitation code detection step of detecting aminimum-run-length limitation code from the input data, theminimum-run-length limitation code being contained in the conversioncodes of the conversion table and limiting the minimum run length d to apredetermined number or less; and a consecutive-minimum-run replacementstep of replacing the codeword string converted by performing theconversion step so that the minimum run length is limited to thepredetermined number or less based on the minimum-run-length limitationcode detected by performing the minimum-run-length limitation codedetection step.

[0045] A program of the present invention causes a computer to execute aconversion step of converting input data into codewords in accordancewith a conversion table containing conversion codes having a coding rulethat the remainder of the number of “1's” in each element of the datasequence divided by two and the remainder of the number of “1's” in eachelement of the converted codeword string divided by two are equally 1 or0; a minimum-run-length limitation code detection step of detecting aminimum-run-length limitation code from the input data, theminimum-run-length limitation code being contained in the conversioncodes of the conversion table and limiting the minimum run length d to apredetermined number or less; and a consecutive-minimum-run replacementstep of replacing the codeword string converted by performing theconversion step so that the minimum run length is limited to thepredetermined number or less based on the minimum-run-length limitationcode detected by performing the minimum-run-length limitation codedetection step.

[0046] In the modulation apparatus and method, and program of thepresent invention, input data is converted into codewords in accordancewith a conversion table containing conversion codes having a coding rulethat the remainder of the number of “1's” in an element of the datasequence divided by two and the remainder of the number of “1's” in anelement of the converted codeword string divided by two are equally 1 or0; a minimum-run-length limitation code contained in the conversioncodes of the conversion table for limiting the minimum run length d to apredetermined number or less is detected from the input data; and thecodeword string into which the input data is converted is replaced sothat the minimum run length is limited to the predetermined number orless based on the detected minimum-run-length limitation code.

BRIEF DESCRIPTION OF THE DRAWINGS

[0047]FIG. 1 is a block diagram showing an example structure of amodulation apparatus of the related art.

[0048]FIG. 2 is a block diagram showing an example structure of anothermodulation apparatus of the related art.

[0049]FIG. 3 is a block diagram showing an example structure of amodulation apparatus according to the present invention.

[0050]FIG. 4 is a diagram illustrating processing of the modulationapparatus shown in FIG. 1.

[0051]FIG. 5 is a block diagram showing a detailed example structure ofthe modulation apparatus.

[0052]FIG. 6 is a block diagram showing another detailed examplestructure of the modulation apparatus.

[0053]FIG. 7 is a schematic diagram showing a register mechanism forconverting an input data sequence to a channel bit string.

[0054]FIG. 8 is a diagram showing a specific example of the operation ofan undefined code detection processor, conversion code detector, andtermination code to which a DSV-control-bit-containing data sequence issupplied from a shift register.

[0055]FIG. 9 is a diagram showing a specific example of the operation ofa minimum-run-length limitation code detection unit for detecting aminimum-run-length limitation code from a data sequence.

[0056]FIG. 10 is a diagram showing the detailed operation of theminimum-run-length limitation code detection unit which refers to amodulation information register to detect a minimum-run-lengthlimitation code.

[0057]FIG. 11 is a diagram showing another example of the detailedoperation of the minimum-run-length limitation code detection unit whichrefers to the modulation information register to detect aminimum-run-length limitation code.

BEST MODE FOR CARRYING OUT THE INVENTION

[0058] An embodiment of the present invention is described below. In thefollowing description, for convenience of illustration, a stream of“0's” and “1's” of unconverted data (unconverted data sequence) isenclosed within parentheses, e.g., (000011), and a stream of “0's” and“1's” of converted code (codeword string) is enclosed within quotationmarks, e.g., “000100100”. Table 2 is an example conversion table of thepresent invention for converting data into code. TABLE 2 1,7PP_table (d,k; m, n; r) = (1, 7; 2, 3; 4) Data Code    11 *0* (Before 0:* = 1,Before 1:* = 0)    10 001    01 010   0011 010 100   0010 010 000   0001000 100  000011 000 100 100  000001 010 100 100 00001000 000 100 100 10000001001 000 100 000 010 00001010 000 100 000 001 00001011 000 100 000101 00000000 010 100 100 100 00000001 010 100 000 010 00000010 010 100000 001 00000011 010 100 000 101 #110111-01  :       001 : 101 010101→001 000 000       00000: 000 010 101 (cbit replace)       0000t:Termination table 00 000 0000 010 100 000010 000 100 000 000000 010 000000

[0059] The conversion table shown in Table 2 is a variable-length tablein which the minimum run length d=1, the maximum run length k=7, thedata-to-channel-bit conversion ratio m:n=2:3, and the maximum constraintlength r=4. This conversion table includes, as conversion codes, a basiccode essential to conversion (code of data sequences (11) to (00000011))and a replacement code which is not essential to conversion but iseffective for conversion (code of data sequence (110111)), and atermination table formed of termination code (code of data sequences(00), (0000), (000010), and (000000)) for terminating a code at anarbitrary position. In the conversion table, a synchronization signal isalso specified.

[0060] In Table 2, an element of the basic code further includes anundefined code (a code containing symbol *) The undefined code is set to“0” or “1” so as to meet the requirement of the minimum run length d andthe maximum run length k, whatever the previous or subsequent codewordstring is. In Table 2, when a 2-bit data sequence to be converted is(11), the 2-bit data sequence is converted into either “000” or “101”depending upon the previous codeword string. If 1 channel bit of theprevious codeword string is set to “1”, the 2-bit data (11) is convertedinto the codeword “000” in order to meet the requirement of the minimumrun length d. If 1 channel bit of the previous codeword string is set to“0”, the 2-bit data (11) is converted into the codeword “101” in orderto meet the requirement of the maximum run length k.

[0061] The conversion table shown in Table 2 also includes a replacementcode for limiting the minimum run length. If the data sequence is(110111), followed by data sequence (01), (001), or (00000), or when thedata sequence (110111) is followed by data sequence (0000) andterminates, then the data sequence (110111) is replaced by the codeword“001000000”. If the data sequence (110111) is not followed by any of theabove-noted data sequences, the data sequence (110111) is encoded inunits of 2 bits ((11), (01), (11)) and is converted into the codewordstring “101010101” or “000010101”.

[0062] The conversion code of Table 2 has a coding rule that theremainder of the number of “1's” in each element of the data sequencedivided by two and the remainder of the number of “1's” in each elementof the converted codeword string divided by two are equally 1 or 0 (thecorresponding elements have an odd- or even-number of “1's”). Forexample, the data sequence element (000001) in the conversion codecorresponds to the codeword string element “010100100”, where the numberof “1's” in the data sequence element is one and the number of “1's” inthe corresponding codeword string element is three. The remainders ofthe number of “1's” in both elements divided by two are equally 1 (oddnumber). Likewise, the data sequence element (00000000) in theconversion code corresponds to the codeword string element“010100100100”, where the number of “1's” in the data sequence elementis zero and the number of “1's” in the corresponding codeword stringelement is four. The remainders of the number of “1's” in both elementsdivided by two are equally 0 (even number).

[0063] An embodiment of the modulation apparatus according to thepresent invention is described with reference to FIG. 3. In thisembodiment, a data sequence is converted into variable-length code (d,k; m, n; r)=(1, 7; 2, 3; 4) in accordance with Table 2.

[0064] As shown in FIG. 3, a modulation apparatus 30 includes a DSVcontrol bit determination and insertion unit 31 for determining “1” or“0”, serving as a DSV control bit, and for inserting the DSV control bitinto an input data sequence at arbitrary intervals; a pattern conversionunit 32 for converting the data sequence containing the determined DSVcontrol bit into a channel bit using a predetermined conversion table; aminimum-run-length limitation code detection unit 33 for detecting, fromthe data sequence containing the DSV control bit, the position ofminimum runs consecutive from the channel bit string converted by thepattern conversion unit 32 and for outputting the resulting positioninformation; a consecutive-minimum-run replacement unit 34 for replacinga predetermined portion of the channel bit string supplied from thepattern conversion unit 32 for a predetermined pattern based on theposition information supplied from the minimum-run-length limitationcode detection unit 33 to limit the minimum run length to apredetermined number or less; a sync signal insertion unit 35 forinserting a synchronization signal at a predetermined position of thechannel bit string supplied from the consecutive-minimum-run replacementunit 34; and an NRZI unit 36 for converting the output of the syncsignal insertion unit 35 into a recording waveform string. Themodulation apparatus 30 further includes a timing management unit 37 forgenerating a timing signal and supplying the timing signal to the DSVcontrol bit determination and insertion unit 31, the pattern conversionunit 32, the minimum-run-length limitation code detection unit 33, theconsecutive-minimum-run replacement unit 34, the sync signal insertionunit 35, and the NRZI unit 36 to manage the timing.

[0065]FIG. 4 is a diagram illustrating processing of the modulationapparatus 30 shown in FIG. 3. The DSV control bit determination andinsertion unit 31 determines and inserts a DSV control bit into a datasequence at arbitrary intervals for each DSV period at which DSV isdetermined. In FIG. 4, the DSV period corresponds to DATA 1, DATA 2, orDATA 3 each having an arbitrary length. As shown in FIG. 4, the DSVcontrol bit determination and insertion unit 31 determines DSV up toDATA 1, in order to first insert a DSV control bit between DATA 1 andDATA 2 of the input data word. DSV is the sum of the values oflevel-coded (NRZI-modulated) channel bit string, into which DATA 1 isconverted, by allocating +1 to the level set to level H (1) and −1 tothe level set to level L (0). The sectional DSV for the next period,i.e., DATA 2, is determined in a similar way. Then, a DSV control bit x1to be inserted between DATA 1 and DATA 2 is determined so that theabsolute values of DSV of DATA 1, the DSV control bit x1, and DATA 2 areclose to “zero”.

[0066] If the DSV control bit x1 is set to (1), the level code of DATA 2subsequent to DATA 1 is inverted. If the DSV control bit x1 is set to(0), the level code of DATA 2 subsequent to DATA 1 is not inverted.Since each of Tables 1 and 2 described above is designed so that theremainder of the number of “1's” in each element of the data sequencedivided by two and the remainder of the number of “1's” in each elementof the converted codeword string divided by two are equally 1 or 0,insertion of (1) into the data sequence corresponds to insertion of “1”into the converted codeword string (in other words, “inversion”).

[0067] After determining the DSV control bit x1 shown in FIG. 4, a DSVcontrol bit x2 is inserted between DATA 2 and DATA 3 at a predetermineddata interval to perform DSV control in a similar way. The DSV at thistime is the DSV of DATA 1, x1, and DATA 2.

[0068] DATA 1 contains a frame synchronization signal (hereinafterreferred to as an FS (Frame Sync)) for synchronization between frames.Thus, DATA 1, which is a DSV period at which the DSV control bit isinserted, has a short duration. The duration of DATA 1 is defined sothat a span 1 of the DSV period indicating the converted channel bitstring including the FS and a channel bit Cbit1 corresponding to DATA 1,a span 2 of the DSV period including a channel bit Cbit2 correspondingto DATA 2, and a span 3 of the DSV period including a channel bit Cbit3corresponding to DATA 3 have the same length (span 1=span 2=span 3).Assuming that the FS has FS (bits) and both DATA 2 and DATA 3 have y(bits), the conversion ratio for the conversion table is expressed asm:n=2:3. Therefore, DATA 1 has y-FS*⅔ (bits). After conversion into thechannel bit string, the DSV control bits become longer by the conversionratio, and the DSV control bits x1, x2, and x3 are changed to Cx1, Cx2,and Cx3, respectively.

[0069] In the channel bit string (NRZI-modulated recording code string),the FS is followed by the DSV control bits at equal intervals, therebyachieving DSV control.

[0070]FIG. 5 is a block diagram showing a detailed example structure ofthe modulation apparatus 30. In FIG. 5, the DSV control bitdetermination and insertion unit 31 inserts a DSV control bit into aninput data sequence, and supplies the resulting data to a shift register51.

[0071] The shift register 51 shifts the data by 2 bits, and supplies thedata to the minimum-run-length limitation code detection unit 33, and anundefined code detection processor 61, a conversion code detector 62,and a termination code detector 63 which are contained in the patternconversion unit 32. The shift register 51 supplies to these componentsbits necessary for the components to perform the respective processing.

[0072] The minimum-run-length limitation code detection unit 33 detectsthe (110111) pattern shown in Table 2 from the input data. Theminimum-run-length limitation code detection unit 33 has a data sequenceof predetermined bits stored therein in advance. When the (110111)pattern is detected from the input data, the minimum-run-lengthlimitation code detection unit 33 further checks the following inputdata sequence. If the (110111) pattern is followed by (01), (001), or(00000), or if the (110111) pattern is followed by (0000) and the inputdata terminates here, the minimum-run-length limitation code detectionunit 33 determines that the minimum-run-length limitation code isdetected, and supplies this information to the consecutive-minimum-runreplacement unit 34.

[0073] Conversely, if (01), (001), or (00000) is detected from the inputdata, or if (0000) is detected from the input data and the input dataterminates here, the minimum-run-length limitation code detection unit33 having a data sequence of predetermined bits stored therein inadvance may check the previous six data bits to the detected pattern inthe input data sequence, and, if the checked data bits are (110111), theminimum-run-length limitation code detection unit 33 may determine thatthe minimum-run-length limitation code is detected, and may supply thisinformation to the consecutive-minimum-run replacement unit 34.

[0074] The undefined code detection processor 61 detects (11) for theconstraint length r=1 shown in Table 2 from the input data. When theinput data includes (11), the undefined code detection processor 61supplies this information to a selector 65 and a conversion patterndetermination unit 66. Then, the undefined code detection processor 61acquires information indicating the last channel bit of the previouspattern from the conversion pattern determination unit 66 or the syncsignal insertion unit 35 (thus, in the modulation apparatus 30, theinformation indicating the last channel bit of the previous pattern isfed back to the undefined code detection processor 61). The undefinedcode detection processor 61 supplies this information to an undefinedbit determination unit 67, so that the undefined bit determination unit67 determines that the detected pattern is to be converted into “101”when the last channel bit is 0 and “000” when the last channel bit is 1.

[0075] The conversion code detector 62 detects other patterns than (11)and (110111) in the portions other than the termination table shown inTable 2. When the data sequence pattern is detected for each of theconstraint lengths r=1 through r=4, the conversion code detector 62supplies this information to the conversion pattern determination unit66.

[0076] The termination code detector 63 detects the termination codepattern in the termination table shown in Table 2. Specifically, if(00), (0000), (000010), or (000000) is detected from the input data andit is determined that information given by an internal terminationposition counter indicates the termination position, the terminationcode detector 63 determines that the termination code is detected, andsupplies this information to the conversion pattern determination unit66. In the modulation apparatus 30, therefore, the termination positionis determined from the data supplied from the shift register 51, thatis, the DSV-control-bit-containing data sequence.

[0077] In FIG. 5, the pattern conversion unit 32 includes, in additionto the above-noted undefined code detection processor 61, conversioncode detector 62, and termination code detector 63, a storage unit 64for storing conversion patterns for the constraint lengths r=1 throughr=4, the selector 65 for selecting a conversion pattern to be used, theconversion pattern determination unit 66 for converting the input datainto channel bits, and the undefined bit determination unit 67 fordetermining undefined bits of the channel bit string.

[0078] The storage unit 64 stores a 2-3 conversion pattern 71 indicatingthe conversion pattern for the constraint length r=1, a 4-6 conversionpattern 72 indicating the conversion pattern for the constraint lengthr=2, a 6-9 conversion pattern 73 indicating the conversion pattern forthe constraint length r=3, and an 8-12 conversion pattern 74 indicatingthe conversion pattern for the constraint length r=4 of the conversiontable shown in Table 2, and supplies these patterns to the selector 65.

[0079] The 2-3 conversion pattern 71, the 4-6 conversion pattern 72, the6-9 conversion pattern 73, and the 8-12 conversion pattern 74 may have adifferent structure from the structure of the correspondence tablebetween the data sequence and the channel bit string shown in Table 2 ifthe information supplied from the undefined code detection processor 61,the conversion code detector 62, the termination code detector 63, orthe minimum-run-length limitation code detection unit 33 includesinformation for individually identifying the elements of the table, forexample, information containing identification information having aone-to-one correspondence with the converted channel bit string.

[0080] The selector 65 selects and obtains a conversion pattern, to beused, from the 2-3 conversion pattern 71, 4-6 conversion pattern 72, 6-9conversion pattern 73, and 8-12 conversion pattern 74 stored in thestorage unit 64 based on the information supplied from the undefinedcode detection processor 61, and supplies the selected pattern to theconversion pattern determination unit 66. When the undefined codedetection processor 61 detects (11) from the input data, the selector 65supplies the 2-3 conversion pattern 71 to the undefined bitdetermination unit 67.

[0081] The conversion pattern determination unit 66 selects conversioncode, to be used, from the conversion patterns supplied from theselector 65 or the undefined bit determination unit 67 based on theinformation acquired from the undefined code detection processor 61, theconversion code detector 62, and the termination code detector 63, andsupplies the selected code to the consecutive-minimum-run replacementunit 34. The conversion pattern determination unit 66 also suppliesinformation indicating the last channel bit of the determined conversionpattern to the undefined code detection processor 61. When the syncsignal insertion unit 35 inserts a synchronization signal into apredetermined position of the channel bit string, the conversion patterndetermination unit 66 supplies to the sync signal insertion unit 35, ifnecessary, termination processing information indicating whether or notthe termination table was used.

[0082] The undefined bit determination unit 67 determines an undefinedcode of the 2-3 conversion pattern 71 supplied from the selector 65based on the information supplied from the undefined code detectionprocessor 61, and supplies this information to the conversion patterndetermination unit 66.

[0083] In the channel bit string output from the pattern conversion unit32, the minimum run length is not limited. The minimum run length islimited by the consecutive-minimum-run replacement unit 34.

[0084] The consecutive-minimum-run replacement unit 34 replaces aparticular portion of the channel bit string supplied from theconversion pattern determination unit 66 based on the informationsupplied from the minimum-run-length limitation code detection unit 33,and limits the minimum run length. Then, the consecutive-minimum-runreplacement unit 34 supplies the channel bit string, whose minimum runlength is limited, to the sync signal insertion unit 35.

[0085] The sync signal insertion unit 35 inserts a synchronizationsignal containing a unique pattern, which does not exist as a conversioncode of the conversion table, into the channel bit string supplied fromthe consecutive-minimum-run replacement unit 34. The sync signalinsertion unit 35 interrupts input of the channel bit string atpredetermined intervals to insert a synchronization signal pattern. Thesynchronization signal pattern inserted in the channel bit string by thesync signal insertion unit 35 has a channel bit string formatdistinguishable from other patterns. The synchronization signal patternis determined by referring to the termination processing informationsupplied, if necessary, from the conversion pattern determination unit66. The sync signal insertion unit 35 inserts the synchronization signalinto the channel bit string, and supplies the channel bit stringcontaining the synchronization signal to the NRZI unit 36. The syncsignal insertion unit 35 also supplies information indicating the lastchannel bit of the synchronization signal inserted in the channel bitstring to the undefined code detection processor 61.

[0086] The termination processing information is supplied from theconversion pattern determination unit 66 to the sync signal insertionunit 35 when the termination pattern (00) or (0000) of the terminationtable shown in Table 2 is detected from the data sequence. Forcompatibility in demodulation, the sync signal insertion unit 35determines whether or not the termination table is used to convert thedata sequence into the channel bit string, and inserts a synchronizationsignal.

[0087] For example, the start channel bit of the synchronization signalis a termination table identification bit, where the termination tableidentification bit is set to 1 when the termination table is used and isset to 0 when a standard table is used. Thus, it is determined whetheror not the termination table is used to convert the data sequence intothe channel bit string.

[0088] The NRZI unit 36 NRZI-modulates the channel bit string suppliedfrom the sync signal insertion unit 35 to rearrange the channel bitstring, in which 1 is inverted and 0 is not inverted, to generate arecording code string. In other words, the channel bit string which hasnot been NRZI-modulated is a bit string indicating the position of theedges of the NRZI-modulated recording code string, and theNRZI-modulated recording code string corresponds to a bit stringindicating the H or L level of recorded data.

[0089] In the foregoing description, the undefined bit determinationunit 67 is provided only for the constraint length r=1: however, thepresent invention is not limited thereto. For example, as shown in FIG.6, undefined bit determination units may be provided for the otherconstraint lengths.

[0090]FIG. 6 is a block diagram showing another detailed examplestructure of the modulation apparatus 30.

[0091] In FIG. 6, the undefined bit determination unit 67 is providedfor the constraint length r=1, an undefined bit determination unit 81 isprovided for the constraint length r=2, an undefined bit determinationunit 82 is provided for the constraint length r=3, and an undefined bitdetermination unit 83 is provided for the constraint length r=4. Thisenables the modulation apparatus 30 to determine undefined bits if theconversion table shown in Table 2 contains undefined codes for all theconstraint lengths r=1, r=2, r=3, and r=4.

[0092] Next, the operation of the modulation apparatus 30 according tothe embodiment described with reference to FIG. 5 is described.

[0093] First, the DSV control bit determination and insertion unit 31inserts a DSV control bit into the input data sequence, and supplies theresulting data to the shift register 51.

[0094]FIG. 7 is a schematic diagram showing a register mechanism forconverting an input data sequence into a channel bit string. FIG. 7illustrates a register mechanism essential to conversion of a datasequence into a channel bit string in accordance with Table 2 describedabove. The register mechanism includes a 12-bit register of data [0:11]for storing the unconverted data sequence containing DSV control bits,and an 18-bit register of cbit [0:17] for storing the converted channelbit string from the pattern conversion unit 32. The register mechanismfurther includes a timing register, etc.

[0095] Referring back to FIG. 5, data of bits necessary for detection,etc., is supplied in units of 2 bits from the shift register 51 to eachof the undefined code detection processor 61, conversion code detector62, and termination code detector 63 of the pattern conversion unit 32,and to the minimum-run-length limitation code detection unit 33.

[0096]FIG. 8 is a diagram showing a specific example of the operation ofthe undefined code detection processor 61, conversion code detector 62,and termination code detector 63 to which the DSV-control-bit-containingdata sequence is supplied from the shift register 51.

[0097] In FIG. 8, the DSV-control-bit-containing data sequence issequentially input to the 12-bit register of data [0:11], starting fromthe data [0], and is shifted towards the higher-numbered registerelements at each clock. The data shifted up to the data [11] isdiscarded at the next shit operation.

[0098] When two data bits are input to the data [0, 1], the undefinedcode detection processor 61, the conversion code detector 62, and thetermination code detector 63 refer to the data [0, 1]. If the data [0,1]=[1, 1], the undefined code detection processor 61 which detects (11)operates in the manner described above, and supplies this information tothe selector 65 and the conversion pattern determination unit 66. Theundefined code detection processor 61 also supplies to the undefined bitdetermination unit 67 information for converting the detected patterninto “101” or “000” based on the last channel bit of the previouspattern obtained from the conversion pattern determination unit 66 orthe sync signal insertion unit 35.

[0099] If the data [0, 1]=[0, 1] or if the data [0, 1]=[1, 0], theconversion code detector 62 which detects (10) or (01) supplies thisinformation to the conversion pattern determination unit 66 so that thedetected pattern is converted into “001” or “010” using the conversioncode for the constraint length r=1 of the conversion table shown inTable 2.

[0100] If the data [0, 1]=[0, 0], the termination code detector 63 whichdetects (00) refers to the internal termination position counter, asdescribed above. If it is determined that the information given by thetermination position counter indicates the termination position, thetermination code detector 63 supplies this information to the conversionpattern determination unit 66, so that the detected pattern is convertedinto “000” and terminates here.

[0101] If the information given by the internal termination positioncounter of the termination code detector 63 does not indicate thetermination position, the pattern (00) is not converted for theconstraint length r=1. If the conversion pattern is not yet determinedwhen two data bits are input to the shift register 51, additional twodata bits are input to the shift register 51.

[0102] When the additional two data bits (total four data bits) areinput, the conversion code detector 62 and the termination code detector63 refer to the data [0, 1, 2, 3]. If the data [0, 1, 2, 3]=[1, 1, 0,0], the data [0, 1, 2, 3]=[0, 1, 0, 0], or the data [0, 1, 2, 3]=[1, 0,0, 0], the conversion code detector 62 which detects (0011), (0010), or(0001) operates in the manner described above, and supplies theinformation to the conversion pattern determination unit 66, so that thedetected pattern is converted into “010100”, “010000”, or “000100” usingthe conversion code for the constraint length r=2 of the conversiontable shown in Table 2.

[0103] If the data [0, 1, 2, 3]=[0, 0, 0, 0], the termination codedetector 63 which detects (0000) refers to the internal terminationposition counter, as described above. If it is determined that theinformation given by the termination position counter indicates thetermination position, the termination code detector 63 supplies thisinformation to the conversion pattern determination unit 66, so that thedetected pattern is converted into “010100” and terminates here.

[0104] If the information given by the internal termination positioncounter of the termination code detector 63 does not indicate thetermination position, the pattern (0000) is not converted for theconstraint length r=2. If the conversion pattern is not yet determinedwhen four data bits are input to the shift register 51, additional twodata bits are input to the shift register 51.

[0105] For the constraint length r=2, only the data [0, 1] may bedetermined since it is already found for the constraint length r=1 thatthe data [2, 3]=[0, 0].

[0106] When the additional two data bits (total six data bits) areinput, the conversion code detector 62 and the termination code detector63 refer to the data [0, 1, 2, 3, 4, 5]. If the data [0, 1, 2, 3, 4,5]=[1, 1, 0, 0, 0, 0] or if the data [0, 1, 2, 3, 4, 5]=[1, 0, 0, 0, 0,0], the conversion code detector 62 which detects (000011) or (000001)operates in the manner described above, and supplies the information tothe conversion pattern determination unit 66, so that the detectedpattern is converted into “000100100” or “010100100” using theconversion code for the constraint length r=3 of the conversion tableshown in Table 2.

[0107] If the data [0, 1, 2, 3, 4, 5]=[0, 0, 0, 0, 0, 0] or if the data[0, 1, 2, 3, 4, 5]=[0, 1, 0, 0, 0, 0], the termination code detector 63which detects (000000) or (000010) refers to the internal terminationposition counter, as described above. If it is determined that theinformation given by the termination position counter indicates thetermination position, the termination code detector 63 supplies thisinformation to the conversion pattern determination unit 66, so that thedetected pattern is converted into “010100000” or “000100000” andterminates here.

[0108] If the information given by the internal termination positioncounter of the termination code detector 63 does not indicate thetermination position, the pattern (000000) or (000010) is not convertedfor the constraint length r=3. If the conversion pattern is not yetdetermined when six data bits are input to the shift register 51,additional two data bits are input to the shift register 51.

[0109] For the constraint length r=3, only the data [0, 1] may bedetermined since it is already found for the constraint length r=2 thatthe data [2, 3, 4, 5]=[0, 0, 0, 0].

[0110] When the additional two data bits (total eight data bits) areinput, the conversion code detector 62 refers to the data [0, 1, 2, 3,4, 5, 6, 7]. If the data [0, 1, 2, 3, 4, 5, 6, 7]=[0, 0, 0, 0, 0, 0, 0,0], the data [0, 1, 2, 3, 4, 5, 6, 7]=[1, 0, 0, 0, 0, 0, 0, 0], the data[0, 1, 2, 3, 4, 5, 6, 7]=[0, 1, 0, 0, 0, 0, 0, 0], or the data [0, 1, 2,3, 4, 5, 6, 7]=[1, 1, 0, 0, 0, 0, 0, 0], or, otherwise, if the data [0,1, 2, 3, 4, 5, 6, 7]=[0, 0, 0, 1, 0, 0, 0, 0], the data [0, 1, 2, 3, 4,5, 6, 7]=[1, 0, 0, 1, 0, 0, 0, 0], the data [0, 1, 2, 3, 4, 5, 6, 7]=[0,1, 0, 1, 0, 0, 0, 0], or the data [0, 1, 2, 3, 4, 5, 6, 7]=[1, 1, 0, 1,0, 0, 0, 0], the conversion code detector 62 which detects (00000000),(00000001), (00000010), or (00000011), or, otherwise, (00001000),(00001001), (00001010), or (00001011) operates in the manner describedabove, and supplies the information to the conversion patterndetermination unit 66, so that the detected pattern is converted into“010100100100”, “010100000010”, “010100000001”, or “010100000101”, or,otherwise, “000100100100”, “000100000010”, “000100000001 ”, or“000100000101” using the conversion code for the constraint length r=4of the conversion table shown in table 2.

[0111] For the constraint length r=4, only the data [0, 1, 2, 3] may bedetermined since it is already found for the constraint length r=2 thatthe data [4, 5, 6, 7]=[0, 0, 0, 0].

[0112] The input DSV-control-bit-containing data sequence is convertedinto a channel bit string in the way described above. The next patternconversion is carried out by, after determining a pattern, returning andrepeating the operation for a constraint length of 1. As shown in FIG.7, data conversion is completed before the channel bit string issupplied from the 18-bit register. The converted channel bit string issupplied to the sync signal insertion 35.

[0113] The minimum-run-length limitation code detection unit 33 refersto the shift register 51, to which the DSV-control-bit-containing datasequence is input, to detect a minimum-run-length limitation code.

[0114]FIG. 9 is a diagram showing a specific example of the operation ofthe minimum-run-length limitation code detection unit 33 for detecting aminimum-run-length limitation code from the data sequence.

[0115] In FIG. 9, like the operation shown in FIG. 8, theDSV-control-bit-containing data sequence is sequentially input to theregister of data [0:11], starting from the data [0], and is shiftedtowards the higher-numbered register elements at each clock. The datashifted up to the data [11] is discarded at the next shift operation.

[0116] Before the minimum-run-length limitation code detection unit 33refers to the register of data [0:11], pattern conversion of the datasequence into the channel bit string is carried out one time in themanner shown in FIG. 8, and the converted channel bit string is storedin the register of the channel bit string cbit [0:17] shown in FIG. 7.

[0117] For the constraint length r=1, if the data [0, 1]=[1, 0), whoseprevious six data bits are represented by the data (2, 3, 4, 5, 6,7]=[1, 1, 1, 0, 1, 1], and a modulation information register meetsconditions, that is, if (01) is detected, the previous six data bitsthereto being (110111), and the modulation information register meetsthe conditions, then, the minimum-run-length limitation code detectionunit 33 determines that the minimum-run-length limitation code isdetected. This information is supplied to the consecutive-minimum-runreplacement unit 34.

[0118] For the constraint length r=2, if the data [0, 1, 2, 3]=[0, 1, 0,0] or the data [0, 1, 2, 3]=[1, 1, 0, 0], whose previous six data bitsare represented by the data [4, 5, 6, 7, 8, 9]=[1, 1, 1, 0, 1, 1], andthe modulation information register meets the conditions, that is, if(0010) or (0011) is detected, the previous six data bits thereto being(110111), and the modulation information register meets the conditions,then, the minimum-run-length limitation code detection unit 33determines that the minimum-run-length limitation code is detected. Thisinformation is supplied to the consecutive-minimum-run replacement unit34.

[0119] For the constraint length r=2, if the data [0, 1, 2, 3]=[0, 0, 0,0], indicating the termination position, whose previous six data bitsare represented by the data [4, 5, 6, 7, 8, 9]=[1, 1, 1, 0, 1, 1], andthe modulation information register meets the conditions, that is, ifthe termination position terminating at (0000) is detected, the previoussix data bits thereto being (110111), and the modulation informationregister meets the conditions, then, the minimum-run-length limitationcode detection unit 33 determines that the minimum-run-length limitationcode is detected. This information is supplied to theconsecutive-minimum-run replacement unit 34.

[0120] For the constraint length r=3, if the data [0, 1, 2, 3, 4, 5]=[0,0, 0, 0, 0, 0] or the data [0, 1, 2, 3, 4, 5][1, 0, 0, 0, 0, 0], whoseprevious six data bits are represented by the data [6, 7, 8, 9, 10,11]=[1, 1, 1, 0, 1, 1], and the modulation information register meetsthe conditions, that is, if (000000) or (000001) is detected, theprevious six data bits thereto being (110111), and the modulationinformation register meets the conditions, then, the minimum-run-lengthlimitation code detection unit 33 determines that the minimum-run-lengthlimitation code is detected. This information is supplied to theconsecutive-minimum-run replacement unit 34.

[0121] The consecutive-minimum-run replacement unit 34 replaces thechannel bit string for a predetermined channel bit string based on theinformation supplied from the minimum-run-length limitation codedetection unit 33. If the data [2, 3, 4, 5, 6, 7]=[1, 1, 1, 0, 1, 1],i.e., if the minimum-run-length limitation code is detected for theconstraint length r=1, the replaced channel bit string is cbit [3, 4, 5,6, 7, 8, 9, 10, 11]. If the data [4, 5, 6, 7, 8, 9]=[1, 1, 1, 0, 1, 1],i.e., if the minimum-run-length limitation code is detected for theconstraint length r=2, the replaced channel bit string is cbit [6, 7, 8,9, 10, 11, 12, 13, 14]. Likewise, if the data [6, 7, 8, 9, 10, 11]=[1,1, 1, 0, 1, 1], i.e., if the minimum-run-length limitation code isdetected for the constraint length r=3, the replaced channel bit stringis cbit [9, 10, 11, 12, 13, 14, 15, 16, 17].

[0122] Accordingly, a channel bit string is replaced by another channelbit string. No additional register is required for replacement, and themodulation apparatus 30 has a simple structure. As shown in FIG. 7, thechannel bit string is replaced before it is supplied from the 18-bitregister. The replaced channel bit string is supplied to the sync signalinsertion unit 35.

[0123] The detailed operation of the minimum-run-length limitation codedetection unit 33 is described with reference to FIG. 10. FIG. 10 is adiagram illustrating the detailed operation of the minimum-run-lengthlimitation code detection unit 33 which refers to the modulationinformation register to detect a minimum-run-length limitation code.

[0124] In FIG. 10, a DSV-control-bit-containing data sequence issequentially input to the register, of which two data bits are convertedinto three channel bits by the pattern conversion unit 32. TheDSV-control-bit-containing data sequence is checked and subjected topattern conversion in units of two data bits in the order of t1, t2, t3,t4, t5, t6, and t7, and is converted into a channel bit string. If thepattern conversion unit 32 is not able to convert theDSV-control-bit-containing data sequence into a channel bit string, anadditional DSV-control-bit-containing data sequence is input, and ischecked and subjected to pattern conversion in units of two data bits(four data bits, six data bits, and eight data bits are checked andsubjected to pattern conversion) in a sequential manner, as describedabove.

[0125] A modulation information register 91 stores 2-bit data. Data isinput bit-by-bit, and a given data bit is shifted when the subsequentdata bit is input. If (11) is detected from theDSV-control-bit-containing data sequence and the detected pattern isconverted into “*0*”, data set to “1” is input to the modulationinformation register 91, and the previous data bit is shifted. If (11)is detected and the detected pattern is not converted into “*0*”, dataset to “0” is input to the modulation information register 91, and theprevious data bit is shifted.

[0126] If both 2 bits stored in the modulation information register 91are “1”, or neither of the 2 bits is input with “0”, theminimum-run-length code detection unit 33 determines that the modulationinformation register 91 meets conditions. The length limitation codereplacement unit 34 replaces the channel bit string, and the 2 bitsstored in the conversion information register 91 are cleared to become“0”

[0127] In FIG. 10, for example, if (11) is detected during t1 from theDSV-control-bit-containing data sequence, (11) is converted into thechannel bit string “000”, as described above. At this time, data set to“1” is input to the modulation information register 91 having initialvalues [0, 0], and the modulation information register 91 has [1, 0].During t2, (11) is detected from the DSV-control-bit-containing datasequence, and (11) is converted into the channel bit string “101”, asdescribed above. At this time, data set to “1” is input to themodulation information register 91, and the data input during t1 isshifted. Thus, the modulation information register 91 has [1, 1].

[0128] During t3, (01) is detected from the DSV-control-bit-containingdata sequence, and (01) is converted into “010”. At this time, noadditional data is input to the modulation information register 91, andthe modulation information register 91 still has [1, 1]. During t4, (11)is detected from the DSV-control-bit-containing data sequence, and (11)is converted into “101”. Thus, data set to “1” is input to themodulation information register 91, and the data input during t1 isshifted. Thus, the modulation information register 91 has [1, 1].

[0129] During t5, (00) is detected from the DSV-control-bit-containingdata sequence. As described above, (00) is not converted, and t5transitions to t6. During t6, (00) is also detected, and t6 transitionsto t7. During t7, (01) is detected, and (000001) is converted into“010100100”. At this time, no additional data is input to the modulationinformation register 91, and the modulation information register 91maintains the previous values. As shown in FIG. 9, theminimum-run-length limitation code detection unit 33 detects (000001)and the previous six data bits which are (110111). Since the modulationinformation register 91 has [1, 1] when the previous six data bits(110111) are detected, the minimum-run-length limitation code detectionunit 33 determines that the minimum-run-length limitation code isdetected. The consecutive-minimum-run replacement unit 34 performschannel-bit-string replacement to replace the channel bit string“101010101” from t2 to t4 for “001000000”.

[0130] After the replacement, in the modulation information register 91,the input data is cleared to become [0, 0].

[0131]FIG. 11 is a diagram showing another example of the detailedoperation of the minimum-run-length limitation code detection unit 33which refers to the modulation information register to detect aminimum-run-length limitation code.

[0132] In FIG. 11, if (00) is detected during t1 from theDSV-control-bit-containing data sequence, (00) is not converted, asdescribed above, and t1 transitions to t2. During t2, (11) is detectedfrom the DSV-control-bit-containing data sequence, and (0011) isconverted into the channel bit string “010100”. At this time, data setto “0” is input to the modulation information register 91 having initialvalues [0, 0], and the modulation information register 91 has [0, 0].

[0133] During t3, (01) is detected from the DSV-control-bit-containingdata sequence, and (01) is converted into “010”. At this time, noadditional data is input to the modulation information register 91, andthe modulation information register 91 maintains the previous values [0,0]. During t4, (11) is detected from the DSV-control-bit-containing datasequence, and (11) is converted into “101”. Thus, data set to “1” isinput to the modulation information register 91, and the data inputduring t2 is shifted. Thus, the modulation information register 91 has[1, 0].

[0134] During t5, (00) is detected from the DSV-control-bit-containingdata sequence. As described above, (00) is not converted, and t5transitions to t6. During t6, (00) is also detected, and t6 transitionsto t7. During t7, (01) is detected, and (000001) is converted into“010100100”. At this time, no additional data is input to the modulationinformation register 91, and the modulation information register 91maintains the previous values. As shown in FIG. 9, theminimum-run-length limitation code detection unit 33 detects (000001)and the previous six data bits which are (110111). Since the modulationinformation register 91 has [1, 0], the minimum-run-length limitationcode detection unit 33 determines that the minimum-run-length limitationcode is not detected. The consecutive-minimum-run replacement unit 34does not replace the channel bit string.

[0135] In the way described above, the minimum-run-length limitationcode detection unit 33 refers to the modulation information register 91to detect a minimum-run-length limitation code.

[0136] This mechanism allows the modulation apparatus 30 to be simplystructured. The minimum-run-length limitation code detection unit 33 andthe consecutive-minimum-run replacement unit 34 are separate from thepattern conversion unit 32, and the modulation apparatus 30 isapplicable to other systems having various specifications.

[0137] For example, in a case where the modulation apparatus 30 isapplied to a system which does not require limitations on the minimumrun length, the minimum-run-length limitation code detection unit 33should be disconnected.

[0138] Distribution media for distributing to users a computer programfor performing the foregoing processes may include recording media suchas magnetic discs, CD-ROMs, and solid-state memory devices, andcommunication media such as networks and satellites.

INDUSTRIAL APPLICABILITY

[0139] According to the modulation apparatus and method of the presentinvention, therefore, a data sequence which is not converted for theconstraint length r=3 is determined and converted for the constraintlength r=4. Furthermore, a minimum-run-length limitation code detectionunit and a consecutive-minimum-run replacement unit are separate from apattern conversion unit. Thus, the modulation apparatus is realized witha simple circuit structure and is easily applicable to other systems.

1. A modulation apparatus for converting data having a basic data lengthof m bits into variable-length code (d, k; m, n; r) having a basic codelength of n bits, said modulation apparatus comprising: conversion meansfor converting input data into codewords in accordance with a conversiontable containing conversion codes having a coding rule that theremainder of the number of “1's” in each element of the data sequencedivided by two and the remainder of the number of “1's” in each elementof the converted codeword string divided by two are equally 1 or 0;minimum-run-length limitation code detection means for detecting aminimum-run-length limitation code from the input data, theminimum-run-length limitation code being contained in the conversioncodes of the conversion table and limiting the minimum run length d to apredetermined number or less; and consecutive-minimum-run replacementmeans for replacing the codeword string converted by the conversionmeans so that the minimum run length is limited to the predeterminednumber or less based on the minimum-run-length limitation code detectedby the minimum-run-length limitation code detection means.
 2. Amodulation apparatus according to claim 1, further comprising modulationinformation storage means for counting the number of conversionsperformed by the conversion means based on a specified conversion codeof the conversion codes contained in the conversion table and forstoring information indicating the conversion count, wherein theminimum-run-length limitation code detection means is controlled todetect the minimum-run-length limitation code from the input data basedon the information stored by the modulation information storage means.3. A modulation apparatus according to claim 2, further comprising:synchronization signal insertion means for inserting a synchronizationsignal containing a unique pattern, which does not exist as a conversioncode of the conversion table, at an arbitrary position into the codewordstring whose minimum run length is limited to the predetermined numberor less by the consecutive-minimum-run replacement means; and NRZIconversion means for NRZI-converting the codeword string in which thesynchronization signal is inserted by the sync signal insertion means togenerate a recording code string.
 4. A modulation apparatus according toclaim 3, wherein the conversion means includes: conversion codedetection means for detecting a predetermined pattern from the inputdata, the predetermined pattern being contained in the conversion codesof the conversion table having a basic code wherein d=1, k=7, m=2, andn=3; termination code detection means for detecting a termination codefrom the input data, the termination code being contained in theconversion codes of the conversion table and terminating a code at anarbitrary position; undefined code detection means for detecting anundefined code from the input data, the undefined code being containedin the conversion codes of the conversion table and containing anundefined code including an undefined character having character “*0*”which becomes “000” or “101”, where * denotes “0” if the previous orsubsequent codeword is “1” and denotes “1” if the previous or subsequentcodeword is “0”; undefined bit determination means for determining avalue of the symbol * of the undefined character contained in theundefined code detected by the undefined code detection means; andconversion pattern determination means for determining the conversioncode of the conversion table to be used, based on the detection resultsof the conversion code detection means, the termination code detectionmeans, and the undefined code detection means, and the value determinedby the undefined bit determination means.
 5. A modulation apparatusaccording to claim 4, wherein the termination code detection meansincludes a termination position counter which supplies information forspecifying the termination position, and the termination code detectionmeans detects a predetermined pattern contained in the conversion codesof the conversion table from the input data, and determines that thetermination code is detected when the information supplied from thetermination position counter indicates the termination position.
 6. Amodulation apparatus according to claim 4, wherein the undefined codedetection means acquires information indicating the last bit of theconversion pattern determined by the conversion pattern determinationmeans and information indicating the last bit of the pattern of thesynchronization signal inserted by the synchronization signal insertionmeans, and the undefined bit determination means determines the value ofthe symbol * of the undefined character based on the informationindicating the last bit of the conversion pattern and the informationindicating the last bit of the pattern of the synchronization signalacquired by the undefined code detection means.
 7. A modulationapparatus according to claim 4, wherein the conversion patterndetermination means determines, based on the termination code, whetheror not the conversion pattern in accordance with which the input datasequence is converted is determined, and the synchronization signalinsertion means inserts the synchronization signal which is subjected topredetermined processing into the codeword string at an arbitraryposition, based on the determination result of the conversion patterndetermination means.
 8. A modulation apparatus according to claim 7,wherein, in the predetermined processing, the start bit of thesynchronization signal is set to “1” if the conversion patterndetermination means determines, based on the termination code, that theconversion pattern is determined, and the start bit of thesynchronization signal is set to “0” if the conversion patterndetermination means determines, based on the termination code, that theconversion pattern is not determined.
 9. A modulation method for amodulation apparatus for converting data having a basic data length of mbits into variable-length code (d, k; m, n; r) having a basic codelength of n bits, said modulation method comprising: a conversion stepof converting input data into codewords in accordance with a conversiontable containing conversion codes having a coding rule that theremainder of the number of “1's” in each element of the data sequencedivided by two and the remainder of the number of “1's” in each elementof the converted codeword string divided by two are equally 1 or 0; aminimum-run-length limitation code detection step of detecting aminimum-run-length limitation code from the input data, theminimum-run-length limitation code being contained in the conversioncodes of the conversion table and limiting the minimum run length d to apredetermined number or less; and a consecutive-minimum-run replacementstep of replacing the codeword string converted by performing theconversion step so that the minimum run length is limited to thepredetermined number or less based on the minimum-run-length limitationcode detected by performing the minimum-run-length limitation codedetection step.
 10. A modulation method according to claim 9, furthercomprising a modulation information storage step of counting the numberof conversions performed in the conversion step based on a specifiedconversion code of the conversion codes contained in the conversiontable and controlling storage of information indicating the conversioncount, wherein, in the minimum-run-length limitation code detectionstep, detection of the minimum-run-length limitation code from the inputdata is controlled based on the information stored by performing themodulation information storage step.
 11. A modulation method accordingto claim 10, further comprising: a synchronization signal insertion stepof inserting a synchronization signal containing a unique pattern, whichdoes not exist as a conversion code of the conversion table, at anarbitrary position into the codeword string whose minimum run length islimited to the predetermined number or less by performing theconsecutive-minimum-run replacement step; and an NRZI conversion step ofNRZI-converting the codeword string in which the synchronization signalis inserted by performing the sync signal insertion step to generate arecording code string.
 12. A modulation method according to claim 11,wherein the conversion step includes: a conversion code detection stepof detecting a predetermined pattern from the input data, thepredetermined pattern being contained in the conversion codes of theconversion table having a basic code wherein d=1, k=7, m=2, n=3; atermination code detection step of detecting a termination code from theinput data, the termination code being contained in the conversion codesof the conversion table and terminating a code at an arbitrary position;an undefined code detection step of detecting an undefined code from theinput data, the undefined code being contained in the conversion codesof the conversion table and containing an undefined code including andefined character having character “*0*” which becomes “000” or “101”,where * denotes “0” if the previous or subsequent codeword is “1” anddenotes “1” if the previous or subsequent codeword is “0”; an undefinedbit determination step of determining a value of the symbol * of theundefined character contained in the undefined code detected byperforming the undefined code detection step; and a conversion patterndetermination step of determining the conversion code of conversiontable to be used, based on the detection results obtained by performingthe conversion code detection step, the termination code detection step,and the undefined code detection step, and the value determined byperforming the undefined bit determination step.
 13. A modulation methodaccording to claim 12, wherein the modulation apparatus includes atermination position counter which supplies information for specifyingthe termination position, and in the termination code detection step, apredetermined pattern contained in the conversion codes of theconversion table is detected from the input data, and it is determinedthat the termination code is detected when the information supplied fromthe termination position counter indicates the termination position. 14.A modulation method according to claim 12, wherein the undefined codedetection step includes controlling acquisition of informationindicating the last bit of the conversion pattern determined byperforming the conversion pattern determination step and informationindicating the last bit of the pattern of the synchronization signalinserted by performing the synchronization signal insertion step, andthe undefined bit determination step includes determining the value ofthe symbol * of the undefined character based on the informationindicating the last bit of the conversion pattern and the informationindicating the last bit of the pattern of the synchronization signalacquired by performing the undefined code detection step.
 15. Amodulation method according to claim 12, wherein, in the conversionpattern determination step, it is determined, based on the terminationcode, whether or not the conversion pattern in accordance with which theinput data sequence is converted is determined, and in thesynchronization signal insertion step, the synchronization signal whichis subjected to predetermined processing is inserted into the codewordstring at an arbitrary position, based on the determination resultobtained by performing the conversion pattern determination step.
 16. Amodulation method according to claim 15, wherein, in the predeterminedprocessing, the start bit of the synchronization signal is set to “1” ifthe conversion pattern determination means determines, based on thetermination code, that the conversion pattern is determined, and thestart bit of the synchronization signal is set to “0” if the conversionpattern determination means determines, based on the termination code,that the conversion pattern is not determined.
 17. A recording mediumhaving a computer-readable program recorded therein, the program beingadapted for a modulation apparatus for converting data having a basicdata length of m bits into variable-length code (d, k; m, n; r) having abasic code length of n bits, the program including: a conversion step ofconverting input data into codewords in accordance with a conversiontable containing conversion codes having a coding rule that theremainder of the number of “1's” in each element of the data sequencedivided by two and the remainder of the number of “1's” in each elementof the converted codeword string divided by two are equally 1 or 0; aminimum-run-length limitation code detection step of detecting aminimum-run-length limitation code from the input data, theminimum-run-length limitation code being contained in the conversioncodes of the conversion table and limiting the minimum run length d to apredetermined number or less; and a consecutive-minimum-run replacementstep of replacing the codeword string converted by performing theconversion step so that the minimum run length is limited to thepredetermined number or less based on the minimum-run-length limitationcode detected by performing the minimum-run-length limitation codedetection step.
 18. A computer-executable program for controlling amodulation apparatus for converting data having a basic data length of mbits into variable-length code (d, k; m, n; r) having a basic codelength of n bits, the program including: a conversion step of convertinginput data into codewords in accordance with a conversion tablecontaining conversion codes having a coding rule that the remainder ofthe number of “1's” in each element of the data sequence divided by twoand the remainder of the number of “1's” in each element of theconverted codeword string divided by two are equally 1 or 0; aminimum-run-length limitation code detection step of detecting aminimum-run-length limitation code from the input data, theminimum-run-length limitation code being contained in the conversioncodes of the conversion table and limiting the minimum run length d to apredetermined number or less; and a consecutive-minimum-run replacementstep of replacing the codeword string converted by performing theconversion step so that the minimum run length is limited to thepredetermined number or less based on the minimum-run-length limitationcode detected by performing the minimum-run-length limitation codedetection step.